In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
SOC data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
However, many SOC designs are increasingly encountering new problem related to the lack of visibility of key interface points in the SOC design. Interface points that were previously externally visible (i.e., accessible) between separate IC chips in earlier designs are now internal points on a single IC chip. This is particularly true of processor buses that interconnect the processor core, memory and peripheral components. Previously, logic analyzers could be coupled directly to the address, data and control lines of processor buses in order to perform debugging and testing procedures.
In new designs, however, these buses are internal to the SOC device. This makes testing and debugging operations more complex. In order to test the operation of an internal bus, the logic analyzer also must be integrated onto the IC chip and the test data must be brought out onto external pins. Unfortunately, this increases the pin-count of the SOC device, an undesirable result.
Therefore, there is a need in the art for improved system-on-a-chip (SOC) devices and other large-scale integrated circuits. In particular, there is a need for improved apparatuses and methods for monitoring transactions on an internal bus in a system-on-a-chip (SOC) device. More particularly, there is a need for improved apparatuses and methods for monitoring transactions on an internal bus in an SOC device without increasing the pin count of the SOC device.